On an NRZ (Non-Return-Zero) signal, a clock is superposed. A SerDes (Serial/Deserializer) circuit extracts data from the input data of the received NRZ signal.
FIG. 1A is a diagram illustrating a fundamental configuration of the SerDes circuit that receives the NRZ signal transmitted from a transmitter. As illustrated in FIG. 1A, the SerDes circuit has a SerDes block 10 and a clock generation block 20. The clock generation block 20 has a PLL circuit 21 that receives a reference clock CLK (27 MHz) and generates a multiplication clock RCLK having a frequency of 2.7 GHz, 100 times 27 MHz.
The SerDes block circuit 10 has a receiving circuit 11, a ⅛ divider 12, and a 1:8 demultiplexer (Demux) 13. The receiving circuit 11 receives input data Din (2.7 Gbps) with RCLK as a sampling clock and outputs a serial data signal. The ⅛ divider 12 divides RCLK into eight parts and outputs a divided clock (337 MHz). The 1:8 Demux 13 converts the serial data signal into 8-bit parallel data based on RCLK and the divided clock and outputs it as output data Dout.
In the SerDes circuit in FIG. 1A, when the receiving circuit 11 takes in input data in synchronization with the rising edge of RCLK, it is desirable for the rising edge of RCLK to be shifted 180 degrees (½ period of the clock) with respect to the change edge of the input data Din. To correct the reception, it is necessary for RCLK to be in a predetermined phase range with respect to this ideal phase.
In the SerDes circuit in FIG. 1A, a clock source on the transmission side that transmits the input data Din and a reference clock source on the reception side that generates CLK are not synchronized, and therefore, it is not possible to receive transmitted data correctly.
Because of this, in the SerDes circuit, data and a clock are separated from the input data Din and the phase of the multiplication clock RCLK applied to the receiving circuit as a sampling clock is adjusted based on the separated clock. The function of recovering a clock from input data is referred to as a CDR (Clock & Data Recovery) function.
FIG. 1B is a diagram illustrating a configuration of the SerDes circuit having the CDR function. As illustrated in FIG. 1B, the SerDes circuit having the CDR function has the SerDes block 10, the clock generation block 20, and a CDR (Clock & Data Recovery) block 30. The SerDes block 10 and the clock generation block 20 are the same as those in FIG. 1A, however, different in that the Demux 13 of the SerDes block 10 outputs an output clock (337 MHz) and takes in input data at SCLKB 180 degrees different in phase from SCLK, to be described later, and outputs it as Bout.
The CDR block 30 detects phase information of the output data Dout and adjusts the phase of the multiplication clock RCLK. As illustrated in FIG. 1B, the CDR block 30 has a digital filter (DF) 31, a PI code generator 32, and a phase interpolator (PI) 33. The DF 31 compares the phase of the change timing of Dout and Bout output from the Demux 13 with the phase of the sampling clock SCLK output from the PI 33 and outputs a phase differential signal, from which the harmonic component is removed through a low pass filter (LPF). LPF is realized by an integral circuit that integrates the result of determination of whether Dout and Bout are advanced or delayed with respect to SCLK by a phase comparator and which substantially performs low pass filtering. The PI code generator 32 generates a PI code to be output to the phase interpolator 33 based on the phase difference signal output from the DF 31. The phase interpolator 33 adjusts the phase of RCLK based on the PI code and outputs the sampling clock SCLK and SCLKB 180 degrees different in phase from SCLK. SCLK and SCLKB are adjusted so as to be in a predetermined phase range with respect to the ideal phase in the receiving circuit 11, as a result.
The SerDes circuit having the CDR function illustrated in FIG. 1B changes the phase of SCLK so as to be in a predetermined phase range with respect to the ideal phase, and therefore, it is possible to correctly receive the input data Din.
As described above, the SerDes circuit having the CDR function is a circuit to recover input data, however, from the viewpoint of the CDR function, it is a circuit for recovering a clock included in input data, and therefore, in some cases, it is referred to as a CDR circuit, and here it also is referred to as a CDR circuit.
FIG. 2 is a flowchart illustrating the functional operation of the SerDes circuit (CDR circuit) having the CDR function.
In step S11, analog blocks, such as the receiving circuit 11, the PI 33, and the PLL 21, are initialized in addition to the blocks, such as the Demux 13, the DF 31, and the PI code generator 21, that perform digital processing.
In step S12, the input data Din is applied.
In step S13, the digital filter (DF) 31 generates a phase difference signal.
In step S14, the PI code generator 32 generates a PI code.
In step S15, the phase interpolator 33 adjusts the phase of RCLK based on the PI code and generates SCLK.
In step S16, whether the phase of SCLK becomes stable and enters a predetermined phase range with respect to the ideal phase is determined and when the state is not stable, the procedure returns to step S13 and when stable, to step S17.
In step S17, that the CDR block 30 becomes stable and the clock phase adjustment is in the locked state is notified to outside.
The CDR circuit is widely known, and therefore, more explanation is omitted.
As described above, the digital filter (DF) 31 generates a phase difference signal from a change edge of recovered data output from the SerDes block. The change edge of the recovered data is determined by a data pattern of input data. Because of this, the data pattern of input data affects the phase difference signal. Specifically, when the input data changes frequently, the change edge occurs frequently in the recovered data, and therefore, the phase difference signal occurs frequently. In contrast to this, when the same data continues in the input data, the frequency of occurrence of change edge is reduced and no phase difference signal occurs for a long period of time, and therefore, a state will continue where in which phase the phase of the sampling clock SCLk is with respect to the ideal phase may not be determined. Because of this, even if there is a very small phase difference between the sampling clock and the clock of the input data, the phase shift is not adjusted but increases gradually and the phase of the sampling clock may extend beyond the predetermined phase range with respect to the ideal phase, i.e., a case in which an unlocked state is brought about. Further, if the phase shift becomes equal to or greater than one period of the clock, an overcycle in which correct data may not be received, i.e., data loss occurs.
It is known that when sampling an analog signal by a sampling signal, if a frequency higher than half the frequency of the sampling signal is included in the analog signal, correct information about the frequency component of the original analog signal may not be obtained. This is referred to as aliasing.
The above-mentioned state where the input data continues to be the same data for a long period of time corresponds to a state where the frequency of occurrence of the change edge is reduced and the frequency of the sampling signal is reduced, i.e., a state where information about the high-frequency clock included in the input data may not be obtained. This state is referred to as an aliasing state.
The SerDes circuit (CDR circuit) having the CDR function used to operate so as to automatically enter the locked state when input data is input and operate as in the locked state even when actually in the aliasing state. Because of this, the SerDes circuit having the CDR circuit used to output erroneous output data even when an overcycle occurs and data may not be received correctly. Erroneous output data adversely affects subsequent processing and reduces the reliability of the SerDes circuit.